When a signal, such as a picture signal which has a large amount of information, is processed at high speed, it is advantageous to separate the signal to be processed into a plurality of sub-signals, each of which is processed in parallel at the same time, and to read out the processed outputs of each separated sub-signal in a short time.
FIG. 3 shows a prior parallel signal processing system. The following description is directed to the final stage of the parallel signal processing to read out the separated parallel results stored in each parallel memory.
In the figure, the numeral 1 (1a-1n) is a signal processing element (called a processor hereinafter) for processing a plurality of separated sub-signals, 2 (2a-2n) is a memory for storing the signal processed by the processor 1, 3 is an address bus for coupling the processor 1 and the memory 2 by an address line (A), a data line (D) and a control line (C), 4 is a host processor for controlling a plurality of element processors, 5 is a selector for selecting the element processor to be connected to the host processor according to the control of the host processor 4, and 6 is a processor unit which includes an element processor 1 and a memory 2. Eight processor units (n=8) are coupled with one another in parallel in the embodiment of FIG. 3.
When the output signals, processed by each processor units 6, are read out, a port of each element processor 1 is selected by the selector 5 sequentially, and the signals in the memories are transferred to the host processor according to the handshake protocol.
However, the prior system has the disadvantages that the signal transfer speed is only 1.5 Mbit/sec (700 nsec) in the typical embodiment, and it takes considerable time to switch the element processors which are the information source. Therefore, when the number of processors 1 in parallel increases, it takes a long time to read out the resultant output signals and the real time, read out is impossible, although the signal processing capability increases. Although a prior direct memory access system would be useful to read out the output signals quickly, the control of that system would be very complicated when the number of parallel processor units 6 is large, and therefore, the total processing speed of the parallel signals decreases.